GS880(E/F)18/32/36C

GS880(E/F)18/32/36C

Part No.

Org.

Operating
Mode

VDD and
I/O
Voltage

FT Access
Time
(ns)

PL
Frequency
(MHz)

Pkg.

Status

Datasheet

Models*

Verilog

BSDL

VHDL

IBIS

GS88036C
SCD

256K x 36

PL/FT

2.5/3.3 V

4.5, 5, 5.5,
6.5, 7.5

333, 300, 250,
200, 150

Prod

n/a

GS88032C
SCD

256K x 32

PL/FT

2.5/3.3 V

4.5, 5, 5.5,
6.5, 7.5

333, 300, 250,
200, 150

Prod

n/a

GS88018C
SCD

512K x 18

PL/FT

2.5/3.3 V

4.5, 5, 5.5,
6.5, 7.5

333, 300, 250,
200, 150

Prod

n/a

GS880E36C
DCD

256K x 36

PL/FT

2.5/3.3 V

4.5, 5, 5.5,
6.5, 7.5

333, 300, 250,
200, 150

Prod

n/a

GS880E32C
DCD

256K x 32

PL/FT

2.5/3.3 V

4.5, 5, 5.5,
6.5, 7.5

333, 300, 250,
200, 150

Prod

n/a

GS880E18C
DCD

512K x 18

PL/FT

2.5/3.3 V

4.5, 5, 5.5,
6.5, 7.5

333, 300, 250,
200, 150

Prod

n/a

GS880F36C
FT ONLY

256K x 36

2.5/3.3 V

4.5, 5, 5.5,
6.5, 7.5

n/a

Prod

n/a

GS880F32C
FT ONLY

256K x 32

2.5/3.3 V

4.5, 5, 5.5,
6.5, 7.5

n/a

Prod

n/a

GS880F18C
FT ONLY

512K x 18

2.5/3.3 V

4.5, 5, 5.5,
6.5, 7.5

n/a

Prod

n/a

*Notes:
Spice models may be requested from our Applications Engineering Department here.
Denali models can be found here.
Synopsys models can be found here.

Features
. FT pin for user-configurable flow through or pipeline operation . Single Cycle Deselect operation (GS88018/32/36C) . Dual Cycle Deselect operation (GS880E18/32/36C) . ZQ mode pin for user-selectable high/low output drive . 2.5 V or 3.3 V +10%/-10% core power supply . 2.5 V or 3.3 V I/O supply	. LBO pin for Linear or Interleaved Burst mode . Internal input resistors on mode pins allow floating mode pins . Byte Write (BW) and/or Global Write (GW) operation . Internal self-timed write cycle . Automatic power-down for portable applications . JEDEC-standard package; available in RoHS-compliant package