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GS8673ET18/36A
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Read Latency
(RL) |
Operating
Frequency
(MHz)
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Verilog |
BSDL |
VHDL |
IBIS |
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2M x 36
4M x 18 |
PL |
1.2/1.3 V VDD;
1.2/1.5 V I/O |
3.0, 2.0
|
600, 450 |
K |
Samples |
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2M x 36
4M x 18 |
PL |
1.2/1.3 V VDD;
1.2/1.5 V I/O |
3.0, 2.0
|
550, 400 |
K |
Samples |
|
|
|
|
|
|
2M x 36
4M x 18 |
PL |
1.2/1.3 V VDD;
1.2/1.5 V I/O |
3.0, 2.0 |
500, 375 |
K |
Samples |
|
|
|
|
|
|
2M x 36
4M x 18 |
PL |
1.2/1.3 V VDD;
1.2/1.5 V I/O |
3.0, 2.0 |
450, 333 |
K |
Samples |
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*Additional Resources:
SPICE models may be requested from our Applications Engineering Department here.
| Features |
.
Simultaneous Read and Write SigmaQuad Interface
. JEDEC-standard package
. Dual Double Data Rate Interface
. Burst of 2 Read and Write
. 1.25 V or 1.35 V core power supply
. 1.2 V to 1.5 V I/O supply |
.
Pipelined Read operation
. Fully coherent Read and Write pipelines
. ZQ mode pin for programmable output drive strength
. IEEE 1149.1 JTAG-compliant Boundary Scan
. 260-Bump, 1 mm bump pitch BGA package |
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