 |
GS8320(E)18/32/36
|
|
|
|
FT Access
Time
(ns) |
|
|
|
|
|
Verilog |
BSDL |
VHDL |
IBIS |
|
1M x 36 |
PL/FT |
2.5/3.3 V |
6.5, 7, 7.5, 8, 8.5, 8.5 |
250, 225, 200, 166, 150, 133 |
GT |
|
|
|
n/a |
|
|
|
1M x 32 |
PL/FT |
2.5/3.3 V |
6.5, 7, 7.5, 8, 8.5, 8.5 |
250, 225, 200, 166, 150, 133 |
GT |
Prod |
|
|
n/a |
|
|
|
2M x 18 |
PL/FT |
2.5/3.3 V |
6.5, 7, 7.5, 8, 8.5, 8.5 |
250, 225, 200, 166, 150, 133 |
GT |
Prod |
|
|
n/a |
|
 |
|
1M x 36 |
PL/FT |
2.5/3.3 V |
6.5, 7, 7.5, 8, 8.5, 8.5 |
250, 225, 200, 166, 150, 133 |
GT |
Prod |
|
|
n/a |
|
|
|
1M x 32 |
PL/FT |
2.5/3.3 V |
6.5, 7, 7.5, 8, 8.5, 8.5 |
250, 225, 200, 166, 150, 133 |
GT |
Prod |
|
|
n/a |
|
|
|
2M x 18 |
PL/FT |
2.5/3.3 V |
6.5, 7, 7.5, 8, 8.5, 8.5 |
250, 225, 200, 166, 150, 133 |
GT |
Prod |
|
|
n/a |
|
|
*Notes:
Spice models may be requested from our Applications Engineering Department here.
Denali models can be found here.
Synopsys models can be found here.
| Features |
.
FT pin for user-configurable flow through or pipeline operation
. Single Cycle Deselect operation (GS832018/32/36)
. Dual Cycle Deselect operation (GS8320E18/32/36)
. ZQ mode pin for user-selectable high/low output drive
. 2.5 V or 3.3 V +10%/-10% core power supply
. 2.5 V or 3.3 V I/O supply |
.
LBO pin for Linear or Interleaved Burst mode
. Internal input resistors on mode pins allow floating mode pins
. Byte Write (BW) and/or Global Write (GW) operation
. Internal self-timed write cycle
. Automatic power-down for portable applications
. JEDEC-standard package; available in RoHS-compliant package
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