 |
|
|
|
|
FT Access
Time
(ns) |
|
|
|
|
|
Verilog |
BSDL |
VHDL |
IBIS |
|
256K x 72 |
PL |
1.8 V VDD;
1.8 V I/O |
n/a |
350, 333, 300, 250 |
C/
GC |
Prod |
|
|
|
|
|
|
512K x 36 |
PL |
1.8 V VDD;
1.8 V I/O |
n/a |
350, 333, 300, 250 |
C/
GC |
Prod |
|
|
|
|
 |
*Notes:
Spice models may be requested from our Applications Engineering Department here.
Denali models can be found here.
Synopsys models can be found here.
| Features |
. Simultaneous Read and Write SigmaQuad Interface
. JEDEC-standard pinout and package
. Double Late Write
. 1.8 V core power supply
. 1.5 V or 1.8 V CMOS I/O supply
. Pipelined Read operation |
. Fully coherent Read and Write pipelines
. ZQ mode pin for programmable output drive strength
. IEEE 1149.1 JTAG-compliant Boundary Scan
. 209-bump BGA package
. RoHS-compliant package available |
|
