 |
|
|
|
|
|
FT
Access
Time
(ns)
|
|
|
|
|
|
|
Verilog
|
BSDL
|
VHDL
|
IBIS |
|
512K x 36 |
PL |
1.8 V VDD;
1.5/1.8 V I/O |
n/a |
357, 333, 300, 250 |
B/
GB |
Prod
|
|
|
|
|
|
|
|
1M x 18
|
PL
|
1.8 V VDD;
1.5/1.8 V I/O
|
n/a
|
357, 333, 300, 250
|
B/
GB
|
|
|
|
|
|
|
*Notes:
Spice models may be requested from our Applications Engineering Department here.
Denali models can be found here.
Synopsys models can be found here.
| Features |
. Simultaneous Read and Write SigmaQuad Interface
. JEDEC-standard pinout and package
. Late Write
. 2.5 V core power supply
. 1.5 V or 1.8 V CMOS I/O supply
. Pipelined Read operation |
. Fully coherent Read and Write pipelines
. ZQ mode pin for programmable output drive strength
. IEEE 1149.1 JTAG-compliant Boundary Scan
. 119-bump BGA package
. RoHS-compliant package available |
|
